Universal FPGS CPLD Kit For Electrical Lab Training

FEATURES ·  It use industries stand Xilinx 9XC108 with 95XC72 ·  It has a serial & parallel (JTAG) link which enable user to communicate with PC. ·  User can develop the circuit/ schematic using Xilinx standard Foundation Series Software and any development tool for VLSI design available in the world. ·  It has I/O counter interface to enable it to connect various demo modules. This helps in man to machine interface. ·  On-chip Flash Program Memory with In-System Programming (ISP)  ·  Can be programmed by the end-user application (IAP) ·  6-clock/12-clock mode Flash bit erasable and programmable via ISP ·  6-clock/12-clock mode programmable “on-the-fly” by SFR bit ·  Peripherals (PCA, timers, UART) may use either 6-clock or ·  12-clock mode while the CPU is in 6-clock mode ·  Speed up to 20 MHz with 6-clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle. ·  Fully static operation ·  Four interrupt priority levels ·  Seven interrupt sources ·  Four 8-bit I/O ports ·  Full-duplex enhanced UART ·  Framing error detection ·  Automatic address recognition ·  Power control modes ·  Clock can be stopped and resumed ·  Idle mode ·  Power down mode ·  Programmable clock-out pin ·  Second DPTR register ·  Asynchronous port reset ·  Low EMI (inhibit ALE) ·  Programmable Counter Array (PCA) ·  PWM ·  Capture/Compare On-board interfaces ·  16x2 LCD module ·  Six Seven Segment Displays ·  Stepper Motor Controller Interface ·  8x8 LED Matrix Display ·  EWSN Status LED's 12 Nos. ·  ADC/DAC Interface ·  RS-232 interface ·  Parallel JTAG interface ·  Four Data Switches ·  Switch Array ·  AT24C16 Serial EEPROM ·  4x4 Keyboard  ·  Power Indicator LED